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<div class="header">
  <div class="summary">
<a href="#func-members">Functions</a>  </div>
  <div class="headertitle"><div class="title">hardware_riscv_platform_timer<div class="ingroups"><a class="el" href="group__hardware.html">Hardware APIs</a></div></div></div>
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<p>Accessors for standard RISC-V platform timer (mtime/mtimecmp), available on Raspberry Pi microcontrollers with RISC-V processors.  
<a href="#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga2afc7ae3feafc019abd3883a3f2fe04f"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__riscv__platform__timer.html#ga2afc7ae3feafc019abd3883a3f2fe04f">riscv_timer_set_enabled</a> (bool enabled)</td></tr>
<tr class="memdesc:ga2afc7ae3feafc019abd3883a3f2fe04f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable or disable the RISC-V platform timer.  <a href="group__hardware__riscv__platform__timer.html#ga2afc7ae3feafc019abd3883a3f2fe04f">More...</a><br /></td></tr>
<tr class="separator:ga2afc7ae3feafc019abd3883a3f2fe04f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacdd646c3b36c51473a16c07a799f9eec"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__riscv__platform__timer.html#gacdd646c3b36c51473a16c07a799f9eec">riscv_timer_set_fullspeed</a> (bool fullspeed)</td></tr>
<tr class="memdesc:gacdd646c3b36c51473a16c07a799f9eec"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configure the RISC-V platform timer to run at full system clock speed.  <a href="group__hardware__riscv__platform__timer.html#gacdd646c3b36c51473a16c07a799f9eec">More...</a><br /></td></tr>
<tr class="separator:gacdd646c3b36c51473a16c07a799f9eec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab016600bb8fc7553da83a90501371693"><td class="memItemLeft" align="right" valign="top">static uint64_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__riscv__platform__timer.html#gab016600bb8fc7553da83a90501371693">riscv_timer_get_mtime</a> (void)</td></tr>
<tr class="memdesc:gab016600bb8fc7553da83a90501371693"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the RISC-V platform timer.  <a href="group__hardware__riscv__platform__timer.html#gab016600bb8fc7553da83a90501371693">More...</a><br /></td></tr>
<tr class="separator:gab016600bb8fc7553da83a90501371693"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga96285c497dceb9126e6ea3130be72bcb"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__riscv__platform__timer.html#ga96285c497dceb9126e6ea3130be72bcb">riscv_timer_set_mtime</a> (uint64_t mtime)</td></tr>
<tr class="memdesc:ga96285c497dceb9126e6ea3130be72bcb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Update the RISC-V platform timer.  <a href="group__hardware__riscv__platform__timer.html#ga96285c497dceb9126e6ea3130be72bcb">More...</a><br /></td></tr>
<tr class="separator:ga96285c497dceb9126e6ea3130be72bcb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga148695c3ff3dce3222934040cfc77d91"><td class="memItemLeft" align="right" valign="top">static uint64_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__riscv__platform__timer.html#ga148695c3ff3dce3222934040cfc77d91">riscv_timer_get_mtimecmp</a> (void)</td></tr>
<tr class="memdesc:ga148695c3ff3dce3222934040cfc77d91"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the current RISC-V platform timer mtimecmp value for this core.  <a href="group__hardware__riscv__platform__timer.html#ga148695c3ff3dce3222934040cfc77d91">More...</a><br /></td></tr>
<tr class="separator:ga148695c3ff3dce3222934040cfc77d91"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7003005e0d2142e95ce53f2ceee29fdd"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__riscv__platform__timer.html#ga7003005e0d2142e95ce53f2ceee29fdd">riscv_timer_set_mtimecmp</a> (uint64_t mtimecmp)</td></tr>
<tr class="memdesc:ga7003005e0d2142e95ce53f2ceee29fdd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set a new RISC-V platform timer interrupt comparison value (mtimecmp) for this core.  <a href="group__hardware__riscv__platform__timer.html#ga7003005e0d2142e95ce53f2ceee29fdd">More...</a><br /></td></tr>
<tr class="separator:ga7003005e0d2142e95ce53f2ceee29fdd"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<p >Accessors for standard RISC-V platform timer (mtime/mtimecmp), available on Raspberry Pi microcontrollers with RISC-V processors. </p>
<p >Note this header can be used by Arm as well as RISC-V processors, as the timer is a memory-mapped peripheral external to the processors. The name refers to this timer being a standard RISC-V peripheral. </p>
<h2 class="groupheader">Function Documentation</h2>
<a id="gab016600bb8fc7553da83a90501371693" name="gab016600bb8fc7553da83a90501371693"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab016600bb8fc7553da83a90501371693">&#9670;&nbsp;</a></span>riscv_timer_get_mtime()</h2>

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<p>Read the RISC-V platform timer. </p>
<dl class="section return"><dt>Returns</dt><dd>Current 64-bit mtime value </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga148695c3ff3dce3222934040cfc77d91">&#9670;&nbsp;</a></span>riscv_timer_get_mtimecmp()</h2>

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<p>Get the current RISC-V platform timer mtimecmp value for this core. </p>
<p >Get the current mtimecmp value for the calling core. This function is interrupt-safe as long as timer interrupts only increase the value of mtimecmp. Otherwise, it must be called with timer interrupts disabled.</p>
<dl class="section return"><dt>Returns</dt><dd>Current value of mtimecmp </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga2afc7ae3feafc019abd3883a3f2fe04f">&#9670;&nbsp;</a></span>riscv_timer_set_enabled()</h2>

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          <td class="memname">static void riscv_timer_set_enabled </td>
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          <td class="paramtype">bool&#160;</td>
          <td class="paramname"><em>enabled</em></td><td>)</td>
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<p>Enable or disable the RISC-V platform timer. </p>
<p >This enables and disables the counting of the RISC-V platform timer. It does not enable or disable the interrupts, which are asserted unconditionally when a given core's mtimecmp/mtimecmph registers are greater than the current 64-bit value of the mtime/mtimeh registers.</p>
<dl class="params"><dt>Parameters</dt><dd>
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    <tr><td class="paramname">enabled</td><td>Pass true to enable, false to disable </td></tr>
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<h2 class="memtitle"><span class="permalink"><a href="#gacdd646c3b36c51473a16c07a799f9eec">&#9670;&nbsp;</a></span>riscv_timer_set_fullspeed()</h2>

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          <td class="paramname"><em>fullspeed</em></td><td>)</td>
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<p>Configure the RISC-V platform timer to run at full system clock speed. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">fullspeed</td><td>Pass true to increment at system clock speed, false to increment at the frequency defined by the system tick generator (the <code>ticks</code> block) </td></tr>
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<h2 class="memtitle"><span class="permalink"><a href="#ga96285c497dceb9126e6ea3130be72bcb">&#9670;&nbsp;</a></span>riscv_timer_set_mtime()</h2>

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          <td class="paramtype">uint64_t&#160;</td>
          <td class="paramname"><em>mtime</em></td><td>)</td>
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<p>Update the RISC-V platform timer. </p>
<p >This function should only be called when the timer is disabled via <a class="el" href="group__hardware__riscv__platform__timer.html#ga2afc7ae3feafc019abd3883a3f2fe04f" title="Enable or disable the RISC-V platform timer.">riscv_timer_set_enabled()</a>. Note also that unlike the mtimecmp comparison values, mtime is <em>not</em> core-local, so updates on one core will be visible to the other core.</p>
<dl class="params"><dt>Parameters</dt><dd>
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    <tr><td class="paramname">mtime</td><td>New value to set the RISC-V platform timer to </td></tr>
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  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga7003005e0d2142e95ce53f2ceee29fdd">&#9670;&nbsp;</a></span>riscv_timer_set_mtimecmp()</h2>

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          <td>(</td>
          <td class="paramtype">uint64_t&#160;</td>
          <td class="paramname"><em>mtimecmp</em></td><td>)</td>
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<p>Set a new RISC-V platform timer interrupt comparison value (mtimecmp) for this core. </p>
<p >This function updates the mtimecmp value for the current core. The calling core's RISC-V platform timer interrupt is asserted whenever the 64-bit mtime value (stored in 32-bit mtime/mtimeh registers) is greater than or equal to this core's current mtime/mtimecmph value.</p>
<dl class="params"><dt>Parameters</dt><dd>
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    <tr><td class="paramname">mtime</td><td>New value to set the RISC-V platform timer to </td></tr>
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